SystemVerilog
#26 6
#27 5
#28 5
#29 5
#30 5
#31 5
#32 4
#33 4
#34 4
#35 4
#36 4
#37 4
#38 4
#39 4
#40 4
#41 3
#42 3
#43 3
#44 3
#45 3
#46 3
#47 3
#48 2
#49 2
#50 2
...